Unterschiede

Hier werden die Unterschiede zwischen zwei Versionen angezeigt.

--- projects:fpga_reverse_engineering [2016/01/20 17:43] – hops
+++ projects:fpga_reverse_engineering [2016/01/27 17:55] (aktuell) – Clock Generator (U21) daniw
@@ Zeile 23: / Zeile 23: @@
 U24
-Pinout:
+Pinout:\\
-CS# - 1 - P31\\
+<code>
-SO  - 2 - P30 (bridge R292)\\
+CS# - 1 - P31
-WP  - 3 - 3.17V\\
+SO  - 2 - P30 (bridge R292)
-GND - 4 - P35\\
+WP  - 3 - 3.17V
-SI  - 5 - P33\\
+GND - 4 - P35
-SCK - 6 - P32\\
+SI  - 5 - P33
-HOLD- 7 - P43\\
+SCK - 6 - P32
-VCC - 8 - P43\\
+HOLD- 7 - P43
+VCC - 8 - P43</code>
 ???: Anobit MSP1040-A0 (ASIC?)\\
@@ Zeile 51: / Zeile 52: @@
 [[http://www.ti.com.cn/cn/lit/ds/symlink/tps54672.pdf|Datenblatt]]\\
 U27
+IDT 844071 (Clock Generator)\\
+[[https://www.idt.com/document/dst/844071-datasheet|Datenblatt]]\\
+U21
 **USB UART:**\\
@@ Zeile 121: / Zeile 126: @@
 Indicates that efuse logic is busy                                         :         0
 </code>
+===== LEDs =====
+  * D3 -> ???
+  * D4 -> AK24
+  * D5 -> AL23
+  * D6 -> AJ14
 ---- dataentry project ----
 type         : project