projects:fpga_reverse_engineering
Unterschiede
Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
Beide Seiten der vorigen RevisionVorhergehende ÜberarbeitungNächste Überarbeitung | Vorhergehende Überarbeitung | ||
projects:fpga_reverse_engineering [2016/01/20 17:41] – hops | projects:fpga_reverse_engineering [2016/01/27 17:55] (aktuell) – Clock Generator (U21) daniw | ||
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Zeile 23: | Zeile 23: | ||
U24 | U24 | ||
- | Pinout: | + | Pinout:\\ |
- | 1 - CS# - P31 | + | < |
- | 2 - SO - P30 (bridge R292) | + | CS# - 1 - P31 |
- | 3 - WP - 3.17V | + | SO |
- | 4 - GND - P35 | + | WP |
- | 5 - SI - P33 | + | GND - 4 - P35 |
- | 6 - SCK - P32 | + | SI |
- | 7 - HOLD- P43 | + | SCK - 6 - P32 |
- | 8 - VCC - P43 | + | HOLD- 7 - P43 |
+ | VCC - 8 - P43</ | ||
???: Anobit MSP1040-A0 (ASIC?)\\ | ???: Anobit MSP1040-A0 (ASIC?)\\ | ||
Zeile 51: | Zeile 52: | ||
[[http:// | [[http:// | ||
U27 | U27 | ||
+ | |||
+ | IDT 844071 (Clock Generator)\\ | ||
+ | [[https:// | ||
+ | U21 | ||
**USB UART:**\\ | **USB UART:**\\ | ||
Zeile 121: | Zeile 126: | ||
Indicates that efuse logic is busy : | Indicates that efuse logic is busy : | ||
</ | </ | ||
+ | |||
+ | ===== LEDs ===== | ||
+ | * D3 -> ??? | ||
+ | * D4 -> AK24 | ||
+ | * D5 -> AL23 | ||
+ | * D6 -> AJ14 | ||
+ | |||
---- dataentry project ---- | ---- dataentry project ---- | ||
type : project | type : project |
projects/fpga_reverse_engineering.1453311684.txt.gz · Zuletzt geändert: 2016/01/20 17:41 von hops