Unterschiede

Hier werden die Unterschiede zwischen zwei Versionen angezeigt.

--- projects:fpga_reverse_engineering [2016/01/17 01:56] – hops
+++ projects:fpga_reverse_engineering [2016/01/27 17:55] (aktuell) – Clock Generator (U21) daniw
@@ Zeile 20: / Zeile 20: @@
 Flash: Micron 25P28V6G (128 MBit Serial Flash)\\
-[[http://www.micron.com/-/media/documents/products/technical%20note/nor%20flash/tn1224_spi_marking.pdf| Datenblatt]]\\
+[[https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/m25p/m25p128.pdf| Datenblatt]]\\
 U24
+Pinout:\\
+<code>
+CS# - 1 - P31
+SO  - 2 - P30 (bridge R292)
+WP  - 3 - 3.17V
+GND - 4 - P35
+SI  - 5 - P33
+SCK - 6 - P32
+HOLD- 7 - P43
+VCC - 8 - P43</code>
 ???: Anobit MSP1040-A0 (ASIC?)\\
@@ Zeile 41: / Zeile 52: @@
 [[http://www.ti.com.cn/cn/lit/ds/symlink/tps54672.pdf|Datenblatt]]\\
 U27
+IDT 844071 (Clock Generator)\\
+[[https://www.idt.com/document/dst/844071-datasheet|Datenblatt]]\\
+U21
 **USB UART:**\\
@@ Zeile 111: / Zeile 126: @@
 Indicates that efuse logic is busy                                         :         0
 </code>
+===== LEDs =====
+  * D3 -> ???
+  * D4 -> AK24
+  * D5 -> AL23
+  * D6 -> AJ14
 ---- dataentry project ----
 type         : project