projects:fpga_reverse_engineering
Unterschiede
Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
Beide Seiten der vorigen RevisionVorhergehende ÜberarbeitungNächste Überarbeitung | Vorhergehende Überarbeitung | ||
projects:fpga_reverse_engineering [2014/09/24 20:28] – Dokumente zu FPGA daniw | projects:fpga_reverse_engineering [2016/01/27 17:55] (aktuell) – Clock Generator (U21) daniw | ||
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Flash: Micron 25P28V6G (128 MBit Serial Flash)\\ | Flash: Micron 25P28V6G (128 MBit Serial Flash)\\ | ||
- | [[http:// | + | [[https:// |
U24 | U24 | ||
+ | |||
+ | Pinout:\\ | ||
+ | < | ||
+ | CS# - 1 - P31 | ||
+ | SO - 2 - P30 (bridge R292) | ||
+ | WP - 3 - 3.17V | ||
+ | GND - 4 - P35 | ||
+ | SI - 5 - P33 | ||
+ | SCK - 6 - P32 | ||
+ | HOLD- 7 - P43 | ||
+ | VCC - 8 - P43</ | ||
???: Anobit MSP1040-A0 (ASIC?)\\ | ???: Anobit MSP1040-A0 (ASIC?)\\ | ||
Zeile 41: | Zeile 52: | ||
[[http:// | [[http:// | ||
U27 | U27 | ||
+ | |||
+ | IDT 844071 (Clock Generator)\\ | ||
+ | [[https:// | ||
+ | U21 | ||
**USB UART:**\\ | **USB UART:**\\ | ||
Zeile 61: | Zeile 76: | ||
</ | </ | ||
**JTAG Pinout:**\\ | **JTAG Pinout:**\\ | ||
- | TDI - AC15\\ | + | TDI - AC15 - P11\\ |
- | TDO - AD14\\ | + | TDO - AD14 - P12\\ |
- | TCK - AB15\\ | + | TCK - AB15 - P10\\ |
- | TMS - AC14\\ | + | TMS - AC14 - P13\\ |
+ | {{: | ||
+ | \\ | ||
+ | **ISE iMPACT output: | ||
+ | Maximum TCK operating frequency for this device chain: 33000000. | ||
+ | Validating chain... | ||
+ | Boundary-scan chain validated successfully. | ||
+ | 1: Device Temperature: | ||
+ | 1: VCCINT Supply: Current Reading: | ||
+ | 1: VCCAUX Supply: Current Reading: | ||
+ | ' | ||
+ | ' | ||
+ | ' | ||
+ | ' | ||
+ | CRC error : 0 | ||
+ | Decryptor security set : | ||
+ | DCM locked | ||
+ | DCI matched | ||
+ | End of startup signal from Startup block : | ||
+ | status of GTS_CFG_B | ||
+ | status of GWE : 1 | ||
+ | status of GHIGH : 1 | ||
+ | value of MODE pin M0 : | ||
+ | value of MODE pin M1 : | ||
+ | Value of MODE pin M2 : | ||
+ | Internal signal indicates when housecleaning is completed | ||
+ | Value driver in from INIT pad : 1 | ||
+ | Internal signal indicates that chip is configured | ||
+ | Value of DONE pin : 1 | ||
+ | Indicates when ID value written does not match chip ID : | ||
+ | Decryptor error Signal | ||
+ | System Monitor Over-Temperature Alarm : 0 | ||
+ | startup_state[18] CFG startup state machine | ||
+ | startup_state[19] CFG startup state machine | ||
+ | startup_state[20] CFG startup state machine | ||
+ | E-fuse program voltage available | ||
+ | SPI Flash Type[22] Select | ||
+ | SPI Flash Type[23] Select | ||
+ | SPI Flash Type[24] Select | ||
+ | CFG bus width auto detection result | ||
+ | CFG bus width auto detection result | ||
+ | Reserved | ||
+ | BPI address wrap around error : 0 | ||
+ | IPROG pulsed | ||
+ | read back crc error : 0 | ||
+ | Indicates that efuse logic is busy : | ||
+ | </ | ||
+ | |||
+ | ===== LEDs ===== | ||
+ | * D3 -> ??? | ||
+ | * D4 -> AK24 | ||
+ | * D5 -> AL23 | ||
+ | * D6 -> AJ14 | ||
---- dataentry project ---- | ---- dataentry project ---- |
projects/fpga_reverse_engineering.1411590529.txt.gz · Zuletzt geändert: 2014/09/24 20:28 von daniw