projects:fpga_reverse_engineering
Dies ist eine alte Version des Dokuments!
FPGA Reverse Engineering
Anobit PC-00007 Board
FPGA: Virtex 5 XC5VLX110T U17
RAM: 5 x Samsung (SEC) K4T1G084QQ (1 GBit DDR2 SDRAM) Datenblatt U11, U13, U18, U22, U25
Flash: Micron 25P28V6G (128 MBit Serial Flash) Datenblatt U24
???: Anobit MSP1040-A0 (ASIC?) U5
RAM: Hynix H27UCG8UDMYR (DDR3 RAM?) Datenblatt U7
USB-UART Bridge: FTDI FT2232HQ Datenblatt U9
Linear LTC2932 (Supply Monitor) Datenblatt U6
Texas Instruments TPS54672 (Schaltregler) Datenblatt U27
USB UART:
Controller wird korrekt erkannt aber die Verbindung wird kurz danach getrennt.
Getestet mit Board nr: 1
dmesg log:
[15653.129591] usb 4-1.2: Detected FT2232H [15653.129595] usb 4-1.2: Number of endpoints 2 [15653.129599] usb 4-1.2: Endpoint 1 MaxPacketSize 512 [15653.129602] usb 4-1.2: Endpoint 2 MaxPacketSize 512 [15653.129606] usb 4-1.2: Setting MaxPacketSize 512 [15653.132535] usb 4-1.2: FTDI USB Serial Device converter now attached to ttyUSB1 [15654.076033] usb 4-1.2: USB disconnect, device number 4 [15654.076453] ftdi_sio ttyUSB0: FTDI USB Serial Device converter now disconnected from ttyUSB0 [15654.076483] ftdi_sio 4-1.2:1.0: device disconnected [15654.076803] ftdi_sio ttyUSB1: FTDI USB Serial Device converter now disconnected from ttyUSB1 [15654.076825] ftdi_sio 4-1.2:1.1: device disconnected
JTAG Pinout:
TDI - AC15
TDO - AD14
TCK - AB15
TMS - AC14
TRST - ???
projects/fpga_reverse_engineering.1411586180.txt.gz · Zuletzt geändert: 2014/09/24 19:16 von hops