projects:fpga_reverse_engineering
Unterschiede
Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
Beide Seiten der vorigen RevisionVorhergehende ÜberarbeitungNächste Überarbeitung | Vorhergehende Überarbeitung | ||
projects:fpga_reverse_engineering [2014/09/24 16:39] – Schaltregler daniw | projects:fpga_reverse_engineering [2016/01/27 17:55] (aktuell) – Clock Generator (U21) daniw | ||
---|---|---|---|
Zeile 3: | Zeile 3: | ||
Anobit PC-00007 Board | Anobit PC-00007 Board | ||
- | FPGA: Virtex 5 XC5VLX110T | + | FPGA: Virtex 5 XC5VLX110T\\ |
+ | [[http:// | ||
+ | [[http:// | ||
+ | [[http:// | ||
+ | [[http:// | ||
+ | [[http:// | ||
+ | [[http:// | ||
+ | [[http:// | ||
+ | [[http:// | ||
+ | [[http:// | ||
U17 | U17 | ||
- | RAM: 5 x Samsung (SEC) K4T1G084QQ (1 GBit DDR2 SDRAM) | + | RAM: 5 x Samsung (SEC) K4T1G084QQ (1 GBit DDR2 SDRAM)\\ |
- | [[http:// | + | [[http:// |
U11, U13, U18, U22, U25 | U11, U13, U18, U22, U25 | ||
- | Flash: Micron 25P28V6G (128 MBit Serial Flash) | + | Flash: Micron 25P28V6G (128 MBit Serial Flash)\\ |
- | [[http:// | + | [[https:// |
U24 | U24 | ||
- | ???: Anobit MSP1040-A0 (ASIC?) | + | Pinout:\\ |
+ | < | ||
+ | CS# - 1 - P31 | ||
+ | SO - 2 - P30 (bridge R292) | ||
+ | WP - 3 - 3.17V | ||
+ | GND - 4 - P35 | ||
+ | SI - 5 - P33 | ||
+ | SCK - 6 - P32 | ||
+ | HOLD- 7 - P43 | ||
+ | VCC - 8 - P43</ | ||
+ | |||
+ | ???: Anobit MSP1040-A0 (ASIC?)\\ | ||
U5 | U5 | ||
- | RAM: Hynix H27UCG8UDMYR (DDR3 RAM?) | + | RAM: Hynix H27UCG8UDMYR (DDR3 RAM?)\\ |
- | [[http:// | + | [[http:// |
U7 | U7 | ||
- | USB-UART Bridge: FTDI FT2232HQ | + | USB-UART Bridge: FTDI FT2232HQ\\ |
- | [[http:// | + | [[http:// |
U9 | U9 | ||
- | Linear LTC2932 (Supply Monitor) | + | Linear LTC2932 (Supply Monitor)\\ |
- | [[http:// | + | [[http:// |
U6 | U6 | ||
- | Texas Instruments TPS54672 (Schaltregler) | + | Texas Instruments TPS54672 (Schaltregler)\\ |
- | [[http:// | + | [[http:// |
U27 | U27 | ||
+ | |||
+ | IDT 844071 (Clock Generator)\\ | ||
+ | [[https:// | ||
+ | U21 | ||
+ | |||
+ | **USB UART:**\\ | ||
+ | Controller wird korrekt erkannt aber die Verbindung wird kurz danach getrennt.\\ | ||
+ | Getestet mit Board nr: 1\\ | ||
+ | |||
+ | **dmesg log:**\\ | ||
+ | < | ||
+ | [15653.129591] usb 4-1.2: Detected FT2232H | ||
+ | [15653.129595] usb 4-1.2: Number of endpoints 2 | ||
+ | [15653.129599] usb 4-1.2: Endpoint 1 MaxPacketSize 512 | ||
+ | [15653.129602] usb 4-1.2: Endpoint 2 MaxPacketSize 512 | ||
+ | [15653.129606] usb 4-1.2: Setting MaxPacketSize 512 | ||
+ | [15653.132535] usb 4-1.2: FTDI USB Serial Device converter now attached to ttyUSB1 | ||
+ | [15654.076033] usb 4-1.2: USB disconnect, device number 4 | ||
+ | [15654.076453] ftdi_sio ttyUSB0: FTDI USB Serial Device converter now disconnected from ttyUSB0 | ||
+ | [15654.076483] ftdi_sio 4-1.2:1.0: device disconnected | ||
+ | [15654.076803] ftdi_sio ttyUSB1: FTDI USB Serial Device converter now disconnected from ttyUSB1 | ||
+ | [15654.076825] ftdi_sio 4-1.2:1.1: device disconnected | ||
+ | </ | ||
+ | **JTAG Pinout:**\\ | ||
+ | TDI - AC15 - P11\\ | ||
+ | TDO - AD14 - P12\\ | ||
+ | TCK - AB15 - P10\\ | ||
+ | TMS - AC14 - P13\\ | ||
+ | {{: | ||
+ | \\ | ||
+ | **ISE iMPACT output: | ||
+ | Maximum TCK operating frequency for this device chain: 33000000. | ||
+ | Validating chain... | ||
+ | Boundary-scan chain validated successfully. | ||
+ | 1: Device Temperature: | ||
+ | 1: VCCINT Supply: Current Reading: | ||
+ | 1: VCCAUX Supply: Current Reading: | ||
+ | ' | ||
+ | ' | ||
+ | ' | ||
+ | ' | ||
+ | CRC error : 0 | ||
+ | Decryptor security set : | ||
+ | DCM locked | ||
+ | DCI matched | ||
+ | End of startup signal from Startup block : | ||
+ | status of GTS_CFG_B | ||
+ | status of GWE : 1 | ||
+ | status of GHIGH : 1 | ||
+ | value of MODE pin M0 : | ||
+ | value of MODE pin M1 : | ||
+ | Value of MODE pin M2 : | ||
+ | Internal signal indicates when housecleaning is completed | ||
+ | Value driver in from INIT pad : 1 | ||
+ | Internal signal indicates that chip is configured | ||
+ | Value of DONE pin : 1 | ||
+ | Indicates when ID value written does not match chip ID : | ||
+ | Decryptor error Signal | ||
+ | System Monitor Over-Temperature Alarm : 0 | ||
+ | startup_state[18] CFG startup state machine | ||
+ | startup_state[19] CFG startup state machine | ||
+ | startup_state[20] CFG startup state machine | ||
+ | E-fuse program voltage available | ||
+ | SPI Flash Type[22] Select | ||
+ | SPI Flash Type[23] Select | ||
+ | SPI Flash Type[24] Select | ||
+ | CFG bus width auto detection result | ||
+ | CFG bus width auto detection result | ||
+ | Reserved | ||
+ | BPI address wrap around error : 0 | ||
+ | IPROG pulsed | ||
+ | read back crc error : 0 | ||
+ | Indicates that efuse logic is busy : | ||
+ | </ | ||
+ | |||
+ | ===== LEDs ===== | ||
+ | * D3 -> ??? | ||
+ | * D4 -> AK24 | ||
+ | * D5 -> AL23 | ||
+ | * D6 -> AJ14 | ||
---- dataentry project ---- | ---- dataentry project ---- |
projects/fpga_reverse_engineering.1411576786.txt.gz · Zuletzt geändert: 2014/09/24 16:39 von daniw